The present invention disclosed herein relates to semiconductor devices that prevent misalignment of interconnections disposed at a small interval and a plug, and methods of manufacturing the same.
Semiconductor devices may be formed to include a plurality of layers such that a plurality of unit devices may be integrated in a semiconductor device. Interconnections may be disposed in a plurality of layers and may be electrically connected to one another. A vertical plug may be formed between layers to electrically connect interconnections. An alignment process is important in order to accurately contact interconnections with the plug connected to the interconnections.
Moreover, as demand for high-integration semiconductor devices increases, space between patterns or interconnections of a semiconductor device is becoming rapidly reduced. As a result, alignment margin is reduced. If misalignment occurs when interconnections formed on different layers are connected to one another, interconnections that must not be connected may be connected. Since the misalignment may cause a malfunction, reliability of a device may be degraded.